In many digital communications applications, it is necessary to sample an input signal to recover data. For example, in high frequency DDR (double data rate) link interfaces, it is necessary to sample the input signal at an optimum time. In some applications, the ideal sample point occurs at a midpoint of a high or low state. Therefore, dividing a cycle accurately is necessary to identify the optimal sampling point.
One conventional sampling circuit determines the sampling points using a fixed time delay. In other words, a sample is taken at a time corresponding to 90 degrees, which is the equivalent of a quarter cycle, after a falling edge or a rising edge of the clock signal. However, this approach does not take into account the fact that clock signals are not ideal.
In some applications, system imperfections may cause the clock signal to be asymmetrical. For example, the high state may be shorter than the low state. If the high state is only 150 degrees instead of 180 degrees, the determination of the midpoint of the high state may be incorrect if the fixed time delay is used. In this case, the midpoint of the high state is 75 degrees rather than 90 degrees after the rising or falling edge of the clock signal. If the sample is taken at 90 degrees from this rising or falling edge, the sample is not taken at the midpoint. In this example, the sample is taken 90 degrees from the rising or falling edge and 60 degrees from the next falling or rising edge, respectively.
One possible inverted-phase detector incorporates a flip-flop circuit that identifies the relative timing of the clock signal and a delayed clock signal. The flip-flop circuit is triggered by the delayed clock signal. For example, if the output of the flip-flop circuit is a “1,” the delayed clock signal is changing state too early with respect to the clock signal. Conversely, if the output of the flip-flop is a “0,” the delayed clock signal is changing state too late with respect to the clock signal.
Flip-flops that are used in this manner have an accuracy within 50-100 picoseconds. The relatively low accuracy of this phase detection circuit typically increases the requirements on other system circuits, which increases the overall cost of system and may reduce yields.